NetNews Offline 2/NetNews Offline Volume 2.iso/news/comp/sys/amiga/hardware-part1/6570/text0000.txt

Text File | 1996-08-05 | 3.7 KB | 88 lines

In article <[e-mail]> [e-mail] (Ola Lidholm) writes:

> I am currently writing a series of articles about the Zorro busses in one
> of the new swedish Amiga Magazines: "Svenska Amiga Magasin".
>
> I have a question about the "DOE" signal in the bus, in "A500/A2000
> technical reference manual" it says that this signal is ment to be used
> to enable the buffers on the expansionsion board (PIC), and also it says
> that the timing on this signal changes if the buscycle is a read or write
> cycle. The "RKRM: Hardware" does not give me any more clues either.
>
> So what I'm wondering is, are there any timing diagrams available where
> you can see exactly how the timg changes, or an exaple as to how you
> actually should use this signal. In the "PIC example" also published in
> the above mentioned book, the signal isn't used at all; it is simply
> stated that that pin (#93) is "reserved".

---What DOE is---

The A500/A2000 Technical Reference manual has some PAL equations for
the bus logic, try page 232, /DBOE equation.
There's a couple of typos (/D5 should be /DS, and the comments in the
/DBOE equation about 'reads' should say 'writes' and vice versa).
(BTW, the TESTRAM PIC PAL equation section also is riddled with typos,
in DBOE, SHUTUP should be /SHUTUP, in PRECON, /AD should be /A4,
and in CONOUT, ASQ should be /ASQ.)

While these seem to be for the A2000 (the early German model), I
assume that the equations are functionally the same for the B2000.

Essentially, DOE gets asserted when AS does on writes,
and on reads, gets asserted when DS and the delayed AS does.
The equations should put this into more detail.

Thus, on a write, DOE gets asserted immediately, since the bus doesn't
have to switch directions.

On a read, DOE only gets asserted when the delayed address strobe
ASQ does, which, from what I understand, is the next 7 MHz cycle
after AS gets asserted.  Thus, this delay gives the CPU time to
switch its bus directions around before your PIC starts to output
its data onto the bus.

You can invert this and use it to control the /OE line on your data
bus buffers to prevent the CPU and the PIC from both attempting to
drive the bus during a read if your AutoConfig logic doesn't
already do this.

---PIC example comments---

The PIC example creates the equivalent of DOE in U9.1
(actually its complement) - the unconnected /Q output
is functionally equivalent to DOE.  You could use DOE instead
of AS_DELAYED*, and change the U3 PAL equations (invert that input
line, which is /ASQ in the equation)
thus eliminating U9.1 entirely.
Of course, in this example, another delay element is specified
for the SRAM, so you don't really save anything by eliminating
U9.1.

For that matter, U4.1 and U4.2 could be eliminated, as the output
of U4.2 is the 7M signal.

This part of the circuit seems to mainly be here for compatibility
with the A500 side expansion port, since it does not have DOE or 7M.
If you'll notice carefully, this is what is required on the
A500 to Zorro II hacks.

---

> I have also heard about a Zorro-III example design "BigRam", that was
> available to developers before commodore whent bancrupt. Is this anything
> that would be available for the public, or do you have to be a registered
> developer?

The only place that I know of where this was published was the
Devcon '91 notes.  Developers had to sign nasty non-disclosure
agreements to get these, and I havn't heard of these becoming
public, so I doubt you'd be able to legitimately get a copy of
these without being a developer.

--
           ________________
Darren    /|        |      \ /  President, Amiga Computer Users of Edmonton
Ewaniuk  /-| |\/| | | |) |  X   email: [e-mail]
HW Eng. /  | |  | | | |\ | / \  www: http://www.ee.ualberta.ca/~ewaniu/
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